<TABLE>
<TR  bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >u_vga_driver</TD>
<TD >18</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >19</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_controller|u_sdram_data</TD>
<TD >32</TD>
<TD >0</TD>
<TD >10</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_controller|u_sdram_cmd</TD>
<TD >90</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >20</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_controller|u_sdram_ctrl</TD>
<TD >24</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >23</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_controller</TD>
<TD >88</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >39</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb</TD>
<TD >10</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|wrfull_eq_comp1_msb</TD>
<TD >10</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rdempty_eq_comp_msb</TD>
<TD >10</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rdempty_eq_comp_lsb</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rdempty_eq_comp1_msb</TD>
<TD >10</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe4</TD>
<TD >13</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|ws_dgrp</TD>
<TD >13</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|ws_bwp</TD>
<TD >13</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|ws_brp</TD>
<TD >13</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe3</TD>
<TD >13</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rs_dgwp</TD>
<TD >13</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|fifo_ram</TD>
<TD >42</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|wrptr_g1p</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|rdptr_g1p</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|ws_dgrp_gray2bin</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated|wrptr_g_gray2bin</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo|dcfifo_component|auto_generated</TD>
<TD >21</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >26</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_rdfifo</TD>
<TD >21</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >26</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb</TD>
<TD >10</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|wrfull_eq_comp1_msb</TD>
<TD >10</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rdempty_eq_comp_msb</TD>
<TD >10</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rdempty_eq_comp_lsb</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rdempty_eq_comp1_msb</TD>
<TD >10</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe3</TD>
<TD >13</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|ws_dgrp</TD>
<TD >13</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe3</TD>
<TD >13</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rs_dgwp</TD>
<TD >13</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rs_bwp</TD>
<TD >13</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rs_brp</TD>
<TD >13</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|fifo_ram</TD>
<TD >42</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|wrptr_g1p</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rdptr_g1p</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rs_dgwp_gray2bin</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated|rdptr_g_gray2bin</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo|dcfifo_component|auto_generated</TD>
<TD >21</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >26</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl|u_wrfifo</TD>
<TD >21</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >26</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top|u_sdram_fifo_ctrl</TD>
<TD >161</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >82</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_sdram_top</TD>
<TD >143</TD>
<TD >120</TD>
<TD >0</TD>
<TD >120</TD>
<TD >40</TD>
<TD >120</TD>
<TD >120</TD>
<TD >120</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_cmos_capture_data</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >17</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_i2c_dri</TD>
<TD >29</TD>
<TD >2</TD>
<TD >0</TD>
<TD >2</TD>
<TD >3</TD>
<TD >2</TD>
<TD >2</TD>
<TD >2</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_i2c_cfg</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >26</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_pll_clk|altpll_component|auto_generated</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >6</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_pll_clk</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE>
